This invention relates to an adapter for bus switch, a bridge for bus switch, and a bus switch and a bus switch system. More particularly, to a bus switch and system, that control, the data transfer on a ring bus with multiple I/O (input/output) ports or data transfer between multiple ring buses.
A conventional data transfer system is composed so that multiple nodes are connected with a bus that allows the two-way communication of data, the nodes, respectively, are connected with multiple modules that conduct different processing, and the data transfer from one module to the other module is conducted. However, in this data transfer system, since data flows in the two directions, the switching control in data transfer such as switching of transfer direction and switching of source and destination, and the extraction of transfer timing are complicated. Therefore, it is difficult to enhance the transfer speed.
Japanese patent application laid-open No. 11-177560 (1999) discloses a data transfer system that enables data to flow in the single direction on the bus.
FIG. 1 shows the data transfer system disclosed in the Japanese patent application laid-open No. 11-177560. In FIG. 1, adapters 902a to 902d are inserted into multiple positions on a ring bus, and the adapters, respectively, are connected with modules 903a to 903d that conduct different processing. The modules 903a to 903d, respectively, conduct various processing, e.g., processing of audio data, processing of image data, input/output processing with the outside of integrated circuit.
The bus 901 has an n bit (n is a natural number) bus width, which is the same as the bit width of data to be transferred. Since the bus 901 is connected in the form of a ring, data is sent, in sequence, from the adapter 902a to the adapter 902b, and then from the adapter 902b to the adapter 902c, and is returned to the adapter 902a from the adapter 902d. Thus, since data is transferred in the one direction (single direction) on the ring bus 901. The switch control of transfer becomes very easy.
FIG. 2 shows one adapter 902 in FIG. 1. Since the adapters 902a to 902d have the same composition, one adapter 902 is explained below taking as an example. The adapter 902 is composed of a flip flop 1001 (D-type flip flop), a data extract/insert circuit 1002 that is connected with the flip flop 1001, a selector 1003 that is connected with the flip flop 1001 and the data extract/insert circuit 1002, and a flip flop 1004 (D-type flip flop) that is connected with the selector 1003.
The flip flop 1001 temporarily stores data to be input from the adjacent adapter (at the previous stage in transfer sequence). The data extract/insert circuit 1002 judges whether the data being input from the flip flop 1001 is addressed to the module 903 connected therewith or not. If the data is sent to the module 903, the data extract/insert circuit 1002 extracts the data, or inserts data when the module 903 thereof outputs the data. The selector 1003 selectively outputs the data from the flip flop 1001 or the data output from the data extract/insert circuit 1002, to the next stage adapter. The selector 1003 has a function to judge whether data being input is addressed to the module connected to itself (its own adapter) or not, a function to send the data to the module connected when the data is addressed to itself and a function to insert data into a time slot transmittable when the data is output from the module connected to itself. The flip flop 1004 holds, with the system clock, data to be output to the bus 901 as the transmission line, and then outputs it to the bus 901.
Data to be transferred through the circuit in FIG. 3 is composed of xe2x80x9cdata entityxe2x80x9d, xe2x80x9cflagxe2x80x9d (to indicate the validity or invalidity of data) added to the head, xe2x80x9cdestination IDxe2x80x9d, and xe2x80x9cclassificationxe2x80x9d. The data extract/insert circuit 1002 reads the fields of xe2x80x9cflagxe2x80x9d and xe2x80x9cdestination IDxe2x80x9d in data, thereby it judges whether data being input is addressed to its own module. When the data input to the flip flop 1001 is addressed to the module 903 of its own, it is transferred to the module 903. When there is data to be output from the module 903 to the bus 901, it conducts the switch control of the selector 1003 so that the module 903 and the flip flop 1004 are communicated with each other.
The operation of the data transfer system having the composition shown in FIGS. 1 and 2 is explained below.
Data output from the flip flop 1004 for re-timing of the adapter 902a is taken into the input-side flip flop 1001 of the next-stage adapter 902b at the next transition timing of system clock. The data taken into the flip flop 1001 is input to the data extract/insert circuit 1002. The data extract/insert circuit 1003 judges, based on the content of the flag and destination ID, whether the data is sent to its own module or not. In this judgement, when it is sent to the module of its own, the type of data is analyzed based on the xe2x80x9cclassificationxe2x80x9d field added to the data, and the data is sent to the module. Simultaneously, when there is a data to be transferred to the other module from the module of its own, xe2x80x9cclassificationxe2x80x9d field and xe2x80x9cdestination IDxe2x80x9d of a module to receive the data are added to the data. Then, setting xe2x80x9cflagxe2x80x9d to indicate that the data is valid, the data is output to the selector 1003. Also, even when there is no data to be transferred, if there is a transferred data in the module of its own, the flag of the data is removed and the data is, as a invalid data, output to the selector 1003. As described above, the data extract/insert circuit 1002 takes data from the flip flop 1001 when its own module 903 is the destination, and switches the selector 1003 to transfer the data from the module 903 to the flip flop 1004 when its own module 903 is the source. Furthermore, when the module 903 is not related to the input/output of data, it switches the input of the selector 1003 to the flip flop 1001, thereby data form the flip flop 1001 is passed toward the flip flop 1004. Data from the flip flop 1004 is input to the next-stage adapter 902c. The other adapters operate in like manner.
Thus, by conducting the data transfer between the flip flop of an adapter and the flip flop of another adapter, the transfer switching control and the extraction of timing can be simplified. In addition, the data transfer between modules can be performed faster.
However, in the conventional data transfer system, when the number of modules connected to one ring bus increases, since the transfer bandwidth (data transfer amount per unit time) of each module is in reverse proportion to the number of modules, the transfer bandwidth of each module becomes small. Also, when the data processing speed of each module cannot follow the data transfer amount, it is necessary to reduce the data transfer speed. Thereby, the efficiency in data transfer lowers.
Accordingly, it is an object of the invention to provide a bus switch adapter, a bus switch bridge, a bus switch and a bus switch system that increases the transfer bandwidth of each module (I/C port) thereby increasing the amount of data transferred per unit time.
It is a further object of the invention to provide a bus switch adapter, a bus switch bridge, a bus switch and a bus switch system that, even when the data processing speed of each module cannot follow the data transfer amount, it is not necessary to lower the data transfer speed.
1) According to the invention, a bus switch adapter for conducting one selected from a data taking operation that extracts data being transferred on a data transferring bus to take the data into a module such as an operating circuit and a transmit/receive circuit, a data inserting operation that inserts data output from the module into the data transferring bus, and a data transferring operation that transfers data on the data transferring bus without conducting the extracting and inserting of data, comprises:
an input register to which parallel data with a given number of bits to be transferred on the data transferring bus is input and which holds the data, the input register being of a given number of parallel bits;
an output register that holds parallel data with a given number of bits and outputs the data to the data transferring bus, the output register being of a given number of parallel bits;
an input storing means that temporarily stores the parallel data held by the input register and outputs the data to the module at a given timing;
an output storing means that temporarily stores the data output from the module and outputs the data, as the parallel data, to the output register at a given timing; and
a control means that controls the outputting of the parallel data from the input register to the input storing means, the outputting of the parallel data from the output storing means to the output register, and the outputting of the parallel data from the input register to the output register.
In this composition, when the data transfer is not conducted between the data transferring bus and the module, the control means controls so that the data is passed through between the input register and the output register. Also, the control means, when the data is transferred from the data transferring bus to the module, controls so that the data taken in the input register is transferred through the input storing means to the module, and, when the data is transferred from the module to the data transferring bus, controls so that the data is stored through the output storing means into the output register and then is output to the data transferring bus at a given timing. Thus, only by locating the adapter at the connection point between each module and the data transferring bus, data is transferred to the post-stage adapter at the clock cycle of register. Therefore, the clock rate in data transfer can be sped up, and even when the number of modules increases the transfer speed on the data transferring bus does not lower. Also, even when the data processing speed of each module cannot follow the data transfer amount, it is not necessary to lower the data transfer speed.
2) According to another aspect of the invention, a bus switch bridge for conducting one selected from a data taking operation that extracts data being transferred on a first data transferring bus to take the data into a second data transferring bus, a data inserting operation that inserts data taken from the second data transferring bus into the first data transferring bus, a data transferring operation that transfers data on the first data transferring bus without conducting the extracting and inserting of data, and a data returning operation that sends data taken from the second data transferring bus back to the second data transferring bus, comprises:
an input register to which parallel data with a given number of bits to be transferred on the first data transferring bus is input and which holds the data, the input register being of a given number of parallel bits;
an output register that holds parallel data with a given number of bits and outputs the data to the first data transferring bus, the output register being of a given number of parallel bits;
an input storing means that temporarily stores the parallel data held by the input register and outputs the data to a first bridge register connected to the second data transferring bus at a given timing;
an output storing means that temporarily stores the data output from a second bridge register connected to second data transferring bus and outputs the data, as the parallel data, to the output register at a given timing; and
a control means that controls the outputting of the parallel data from the input register to the input storing means, the outputting of the parallel data from the output storing means to the output register, and the outputting of the parallel data from the second bridge register to the first bridge register.
In this composition, when the data transfer is not conducted between the first data transferring bus and the second data transferring bus, the control means controls so that the data is passed through between the input register and the output register. Also, the control means, when the data is transferred from the first data transferring bus to the second data transferring bus, controls so that the data taken in the input register is transferred through the input storing means and the first bridge register to the second data transferring bus, and, when the data is transferred from the second data transferring bus to the first data transferring bus, controls so that the data is stored through the second bridge register and the output storing means into the output register and then is output to the first data transferring bus from the output register. Thus, only by locating the bridge at the connection point between the first data transferring bus and the second data transferring bus, the connection with the other ring bus is enabled, therefore the modules can be distributed to the other data transferring bus through the bridge. As a result, even when the number of modules connected to the bus increases, the transfer bandwidth of each module does not reduce, therefore the data transfer speed does not lower.
3) According to another aspect of the invention, provided is a bus switch for extracting data being transferred on a data transferring bus to input the data through an adapter to a module such as an operating circuit and a transmit/receive circuit, and for inserting data output from the module into the data transferring bus through the adapter, wherein the adapter comprises:
an input register to which parallel data with a given number of bits to be transferred on the data transferring bus is input and which holds the data, the input register being of a given number of parallel bits;
an output register that holds parallel data with a given number of bits and outputs the data to the data transferring bus, the output register being of a given number of parallel bits;
an input storing means that temporarily stores the parallel data held by the input register and outputs the data to the module at a given timing;
an output storing means that temporarily stores the data output from the module and outputs the data, as the parallel data, to the output register at a given timing; and
a control means that controls the outputting of the parallel data from the input register to the input storing means, the outputting of the parallel data from the output storing means to the output register, and the outputting of the parallel data from the input register to the output register.
In this composition, when the data is transferred from the data transferring bus to the module, the data taken in the input register is transferred through the input storing means to the module, and, when the data is transferred from the module to the data transferring bus, the data is stored through the output storing means into the output register and then is output to the data transferring bus. Thus, the data transfer to/from the data transferring bus is conduced through the register. Therefore, the clock rate in data transfer can be sped up. Also, even when the data processing speed of each module cannot follow the data transfer amount, it is not necessary to lower the data transfer speed.
4) According to another aspect of the invention, provided is a bus switch system for connecting a first data transferring bus and a second data transferring bus through a bridge and for transferring data between the first data transferring bus and the second data transferring bus, wherein the bridge comprises:
an input register to which parallel data with a given number of bits to be transferred on the first data transferring bus is input and which holds the data, the input register being of a given number of parallel bits;
an output register that holds parallel data with a given number of bits and outputs the data to the first data transferring bus, the output register being of a given number of parallel bits;
an input storing means that temporarily stores the parallel data held by the input register and outputs the data to a first bridge register connected to the second data transferring bus at a given timing;
an output storing means that temporarily stores the data output from a second bridge register connected to second data transferring bus and outputs the data, as the parallel data, to the output register at a given timing; and
a control means that controls the outputting of the parallel data from the input register to the input storing means, the outputting of the parallel data from the output storing means to the output register, and the outputting of the parallel data from the second bridge register to the first bridge register.
In this composition, when the data is transferred from the first data transferring bus to the second data transferring bus, the data taken in the input register of the bridge is transferred through the input storing means and first bride register is the second data transferring bus. Also, when the data is transferred from the second data transferring bus to the first data transferring bus, the data taken in the first bridge register is transferred through the output storing means and the output register to the first data transferring bus. Thus, the data transfer between the first and second data transferring buses is conduced through the register. Therefore, the clock rate in data transfer can be sped up, and even when the number of modules connected on the first data transferring bus increases, the transfer speed does not lower. Further, even when the number of modules connected to the first data transferring bus comes to the limit, arbitrary number of buses can be connected each other. This gives such a state as one big ring bus is formed. Therefore, neither the transfer speed nor the transfer bandwidth lowers.
5) According to another aspect of the invention, provided is a bus switch system for connecting, through a bridge, a first data transferring bus and a second data transferring bus that transfer data to be extracted and inserted from a module such as an operating circuit and a transmit/receive circuit through an adapter, wherein,
the adapter comprises a first input register to which parallel data with a given number of bits to be transferred on the first data transferring bus is input and which holds the data, the first input register being of a given number of parallel bits: a first output register that holds parallel data with a given number of bits and outputs the data to the first data transferring bus, the first output register being of a given number of parallel bits; a first input storing means that temporarily stores the parallel data held by the first input register and outputs the data to the module at a given timing; a first output storing means that temporarily stores the data output from the module and outputs the data, as the parallel data, to the first output register at a given timing; and a control means that controls the outputting of the parallel data from the first input register to the first input storing means; the outputting of the parallel data from the first output storing means to the first output register, and the outputting of the parallel data from the first input register to the first output register; and
the bridge comprises: a second input register to which parallel data with a given number of bits to be transferred on the first data transferring bus is input and which holds the data, the second input register being of a given number of parallel bits; a second output register that holds parallel data with a given number of bits and outputs the data to the first data transferring bus, the second output register being of a given number of parallel bits; a second input storing means that temporarily stores the parallel data held by the second input register and outputs the data to a first bridge register connected to the second data transferring bus at a given timing, a second output storing means that temporarily stores the data output from a second bridge register connected to second data transferring bus and outputs the data, as the parallel data, to the second output register at a given timing; and a control means that controls the outputting of the parallel data from the second input register to the second input storing means, the outputting of the parallel data from the second output storing means to the second output register, the outputting of the parallel data from the first input register to the second output register, and the outputting of the parallel data from the second bridge register to the first bridge register.
In this composition, with the adapter, when the data is transferred from the first data transferring bus to the module, the data taken in the first input register is transferred through the first input storing means to the module. Also, when the data is transferred from the module to the first data transferring bus, the data is stored through the first output storing means into the first output register and then is output to the first data transferring bus.
With the bridge, when the data is transferred from the first data transferring bus to the second data transferring bus, the data taken in the second input register of the bridge is transferred through the second input storing means and first bride register to the second data transferring bus. Also, when the data is transferred from the second data transferring bus to the first data transferring bus, the data taken in the first bridge register is transferred through the second output storing means and the second output register to the first data transferring bus.
Thus, the data transfer on the first data transferring bus and between the first and second data transferring buses is conduced through the register. Therefore, the clock rate in data transfer can be sped up, and even when the number of modules connected on the first data transferring bus increases or even when the data transfer is conducted among multiple buses, the transfer speed does not lower. Further, even when the number of modules connected to the first data transferring bus comes to the limit, arbitrary number of buses can be connected each other. This gives such a state as one big ring bus is formed. Therefore, neither the transfer speed nor the transfer bandwidth lowers. Also, even when the data processing speed of each module cannot follow the data transfer amount, it is not necessary to lower the data transfer speed.